1. Field of the Invention
This invention relates to a digital signal transmission apparatus, and more particularly to a transmission line switching method for a digital signal transmission apparatus having a synchronous digital hierarchy (SDH) interface specified in the CCITT Recommendation G.707, G.708 and G.709.
2. Description of the Related Art
Conventionally, in a transmission line switching method for a transmission apparatus of the type mentioned, when the synchronous transfer mode (STM) level exhibits an abnormal level continuously for a fixed period of time, that is, when the rate of code errors of a receive signal detected by supervision of a section overhead (SOH) exhibits a level higher than a certain threshold level for more than the fixed period of time, switching using an automatic protection switching (APS) byte of the section overhead (SOH) is performed in accordance with the CCITT Recommendation G.783.
Further, in a SDH interface, the following method is employed as a code error detection method for a VC-3 signal (VC bit rate: 48.960 Mb/s) or a VC-4 signal (VC bit rate: 150.336 Mb/s) which is a high order virtual container.
In an apparatus which produces and sends out a VC-3 signal or a VC-4 signal, a bit interleaved parity of 8 bits (BIP-8) is calculated in units of a frame, and a result of the calculation is inserted into a B3 byte of a path overhead (POH) of a next frame as illustrated in FIG. 4. In an apparatus for receiving such VC-3 or VC-4 signal, a BIP-8 is calculated in units of a frame, and a result of the calculation and a B3 byte of a next frame are compared with each other to detect a code error in units of a frame.
As one of switching systems for a digital transmission line whose application is not limited only to a SDH transmission apparatus, a system disclosed in, for example, Japanese Patent Laid-Open Application No. Showa 61-247142 is known. FIG. 3 illustrates the digital transmission line switching system disclosed in the publication mentioned above.
A 0 system channel supervisory circuit 101 which is a working system used at present and a 1 system channel supervisory circuit 102 which serves as a protection system supervise receive signals of a 0 system transmission line or channel and a 1 system transmission line or channel, respectively. A phase synchronization section 103 synchronizes the phases of frames and bits of the two signals and outputs the two signals in a same phase to a selector 104. A selector control section 105 switches the selector 104 in response to control signals from the 0 system channel supervisory circuit 101 and the 1 system channel supervisory circuit 102. In particular, when an abnormal condition is detected by the 0 system channel supervisory circuit 101, the selector 104 selects the receive signal of the 1 system channel, but when an abnormal condition such as a code error is detected by the 1 system channel supervisory circuit 102, the selector 104 selects the receive signal of the 0 system channel. Since the phases of the signals inputted by way of the two channels to the selector 104 are coincident with each other, the output of the selector 104 does not exhibit a phase jump upon switching.
However, where the conventional switching system described above is applied to a transmission apparatus having a SDH interface, that is, where objects for synchronizing in phase are VC-3 or VC-4 signals and parity calculation (BIP-8) in units of a frame of a VC-3 or VC-4 signal is employed as supervisory means for a channel, even if a code error occurs in a channel which is currently selected by the selector, such code error cannot be detected until after a parity calculation for the one frame is completed. Consequently, before the code error is detected actually, the VC-3 or VC-4 frame which includes the code error is outputted from the selector, and an apparatus connected at the next stage receives the signal which includes the code error although interruption of the receive signal which may be caused by a phase jump upon switching does not take place.